Title of Seminar:
“Chip-Package Co-design and Analysis for High-performance and Low Noise 3D Semiconductor Systems”
Tutorial Schedule: Total 2 hours
Tutorial Date: 4:15 pm-6pm, October 2 (Thursday), 2008
Tutorial Site: Kyungpook University, E10-313
Speaker: Prof. Joungho Kim
joungho@ee.kaist.ac.kr
Speaker Affiliation: Terahertz Interconnection and Package Laboratory
KAIST
Abstract of Seminar:
In order to meet intensively growing needs of low cost and extremely small form-factor semiconductor system solutions for high-density and multi-function mobile multimedia, computing, and communication system platforms, 3D system IC’s and packages are becoming even popular design approaches. However, significant integration of multiples chips in three dimensional stacking structures with a multi-layer substrate inevitably yields strong concerns on signal integrity and power integrity issues of the integrated system, while clock speeds of the digital chips are steadily increasing and noise sensitive analog and RF circuits are contained into a single package. The problem can be even serous in 3D IC or package based on vertical TSV type interconnections.
In this tutorial, new design and analysis approaches will be introduced with the consideration of the signal integrity and power integrity at the 3D high speed and low noise semiconductor systems. The unique methods are based on simultaneous and hierarchical chip-package co-design and modeling in order to offer cost effective design solutions at high-speed IO, clock delivery network, and Power Distribution Network (PDN). In particular, several investigations will be discussed, in which we can observe high-frequency electromagnetic interactions between the chips and packages through IO channel and PDN, which could be critical design considerations to ensure secure and reliable operations of the systems. Finally, numerous modeling design, and study results will be presented with measurements, especially for the cases of OpAmp, LNA, and Mixer in SiP.
Tutorial Outline:
Part I: Chip-Package Co-design and Analysis for Signal Integrity (1 hour)
I.1 High frequency channel loss
I.2 High frequency model for 3D TSV-based IC interconnections
I.3 Hybrid equalization design and measurement
I.4 Chip-package Co-design of 3D clock distribution networks
Part II: Chip-Package Co-design and Analysis for Power Integrity (1 hour)
II.1 Chip-package hierarchical PDN co-modeling and simulation
II.2 Chip-package PDN interactions at OpAmp, LNA and Mixer in SiP
II. 3 PDN in TSV-based 3D IC
Joungho Kim
Joungho Kim received B.S. and M.S. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 1984 and 1986, respectively, and Ph.D degree in electrical engineering from the University of Michigan, Ann Arbor, in 1993. In 1994, he joined Memory Division of Samsung Electronics, where he was engaged in Gbit-scale DRAM design.
In 1996, he moved to KAIST (Korea Advanced Institute of Science and Technology). He is currently a Professor at Electrical Engineering and Computer Science Department. Since joining KAIST, his research centers on modeling, design, and measurement methodologies of 3D hierarchical semiconductor systems including multi-stack high-speed chip, 3D package, interconnection, and multi-layer PCB. Especially, his major research topic is focused on chip-package co-design and simulation for signal integrity, power integrity, ground integrity, timing integrity, and radiated emission in 3D IC, 3D semiconductor packages, and SiP(System-in-package). He has successfully demonstrated low noise and high performance designs of more than 10 SiP’s for wireless communication applications such as ZigBee, T-DMB, NFC, and UWB. He was on a sabbatical leave during an academic year from 2001 to 2002 at Silicon Image Inc., Sunnyvale CA. He was responsible for low noise package designs for SATA, FC, HDMI, and Panel Link SerDes devices. Currently, he is the director of Satellite Research Laboratory of Hyundai Motors Inc. for EMI/EMC modeling of automotive RF, power electronic and cabling systems.
He has authored and co-authored over 230 technical papers published at refereed journals and conference proceedings in modeling, design, and measurement of 3D IC, package, and SiP. Also, he has given more than 105 invited talks and tutorials at the academia and the related industries. He has received Outstanding Academic Achievement Faculty Award of KAIST in 2006, and Best Faculty Research Award of KAIST in 2008. Dr. Joungho Kim is the symposium chair of IEEE EDAPS 2008 Symposium. Currently, he is an Associated Editor of the IEEE Transactions of Electromagnetic Compatibility. He also serves as the chapter chair of IEEE CPMT Daejon Chapter.
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