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1. 제 목 : Diffusion Barriers for Advanced Copper Metallization
2. 발 표 자 : 김수현 교수(영남대 공과대학 신소재공학부)
3. 일 시 : 2009. 1. 7(수) 14:00~16:00
4. 장 소 : 공대 11호관 103호
5. 초청교수 : 함성호 교수(경북대 전자전기컴퓨터학부)
6. 내용요약
Cu metallizations in logic devices have been extensively studied for more than 20 years and the integration of Cu interconnects into commercial logic devices has been successfully achieved. However, little work has been done on the evaluation of their validities in memory devices such as DRAM and NAND Flash. It should be noted that a different interconnect scheme can be applied when the Cu interconnect is integrated into memory devices. This is because the fabrication of memory devices requires a more cost-effective solution as compared to that of logic devices. One of the promising options for the interconnect structure in memory devices is to use a Cu interconnect with an Al interconnect. As one part of this talk, I will report the diffusion barrier performances and failure mechanisms of transition metal nitride thin films, including TiNx,TaNx, and WNx, between Al and Cu deposited by IPVD (ionized physical vapor deposition) or ALD (atomic layer deposition), which is particularly important for the integration of the Cu interconnect in to memory devices.
As semiconductor devices are scaled down for better performance and more functionality, the Cu-based interconnects suffer from the increase of the resistivity of the Cu wires due to the size effect on the resistivity of the metal film. This problem can be overcome by increasing the volume of electro-plated (EP) copper filled into trench, which can be obtained by direct plating of Cu. Recently, Ru has been suggested as a diffusion barrier that is compatible with the direct plating of Cu. However, previous studies have shown that the Ru by itself is not a suitable diffusion barrier for Cu metallization. Thus, as the second part of this talk, we report the bilayer diffusion barrier of Ru/TaCN prepared by ALD. From this study, we suggest that the bilayer diffusion barrier of Ru/TaCN is a viable candidate for the seed layer/diffusion barrier for direct-plateable Cu interconnects.
※ 주최 : 반도체공정교육 및 지원센터(NECST), 디스플레이기술교육센터(DTEC)
■ 문의처 : 반도체공정교육 및 지원센터(NECST) ☎ 053-950-7591 ■
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