1. 제 목 : Low power/high speed pipeline CMOS ADC design techniques
2. 발 표 자 : 국윤재 박사(Oregon State University)
3. 일 시 : 2007. 12. 28(금) 16:30~18;30
4. 장 소 : 공대5호관 104호
5. 초청교수 : 이종호 교수
6. 강사약력
He received the B.S. degree in electrical engineering from Korea Advanced Institute of Science
and Technology (KAIST), Daejeon, in 1996. He received the M.S. and Ph.D. degrees from Seoul
National University (SNU), Seoul, in 1998 and 2003, respectively, all in electrical engineering.
From 2003 to 2006, he worked at Oregon State University, Corvallis, OR as a visiting scholar.
In 2006, he joined Rockwell Scientific (now, Teledyne Scientific), Thousand Oaks, CA.
7. 내용요약
Low power/high speed ADC''''s are critical components in many applications, especially in portable devices. Some new techniques are proposed and discussed.
At first, Time-aligned/shifted CDS (correlated double sampling) technique is proposed. While the conventional CDS technique needs three phases, time-aligned/shifted CDS needs two phases, so is suitable for high-speed operation.
At second, Opamp and capacitor sharing technique is proposed. By sharing feedback capacitor and sampling capacitor of the next stage, effective load of an opamp is drastically reduced, so is suitable for low-power operation.
※ 주최 : BK21 정보기술연구인력양성사업단, 반도체공정교육 및 지원센터(NECST)
■ 문의처 : 반도체공정교육 및 지원센터(NECST) ☎ 950-7591 ■
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