1. 제 목 : Physical Design for 3D Integration at the Chip and Package
Level
2. 발 표 자 : 임 성 규 (Georgia Institute of Technology, 부교수)
3. 일 시 : 2008년 5월 16일(금) 14 : 00 - 18 : 00
4. 장 소 : 공대11호관 103호
5. 초청교수 : 최두현 교수
6. 강사약력 :
- 1994 : University of California, Los Angeles (UCLA), B.S. degree
- 1997 : UCLA, M.S. degree
- 2000 : UCLA, Ph.D. degree
- 2000 ~ 2001 : UCLA Post-Doctorial scholar &
Senior Engineer at Aplus Design Technologies, Inc
- 2001 ~ : Georgia Institute of Technology, Associate Professor
7. 내용요약 :
In this talk, we present our recent research accomplishments on two promising technologies for 3D integration, namely, 3D stacked IC and 3D embedded passives. The 3D IC is an emergent technology that vertically stacks multiple die with die-to-die interconnects. This results in a decrease in the overall wire length, which translates into less wire delay and less power. Embedded passive is an emergent technology that has a potential for increased reliability, improved electrical performance, size shrinkage and reduced cost. Using this technology, surface-mount passive components used in systems can be integrated into packaging substrate via multiple layers.
※ 주최 : BK21 정보기술연구인력양성사업단, 전자전기컴퓨터학부
◀ 문의처 : BK21정보기술연구인력양성사업단 ☎ 950-6613 ▶
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